Bipolar transistors are widely employed for switching and amplification of electrical signals in modern semiconductor devices. Such bipolar devices are found in products fabricated using bipolar and BiCMOS processing techniques, which integrates bipolar and CMOS technology. In a BiCMOS device, bipolar transistors are often used for analog signal processing and conditioning, whereas MOS devices are employed for digital signals. NPN bipolar transistors comprise a p-type base situated between an n-type emitter and an n-type collector, whereas PNP type bipolar transistors include an n-type base between a p-type emitter and a p-type collector. Under a forward bias, an NPN collector is at a higher potential than the emitter. Very little electron current flows from the emitter to the collector unless there is a base current. A small base current induces significant electron current to flow from the emitter to the collector. The ratio of the emitter current to the base current is referred to as the transistor gain beta. Thus, the beta or gain of a bipolar transistor is an important performance parameter, and semiconductor manufacturers strive to fabricate devices having consistent and repeatable betas from lot to lot, as well as matched betas within a single device.
Transistor emitter area is another parameter that is important and-requires careful control in high performance analog circuits. Currents in various stages of amplifiers are set by current mirrors, which often are strongly dependent on emitter area ratios. Mismatches manifest themselves as input offsets and increased distortion in the amplifier characteristics. Other circuit topologies such as variable gain amplifiers depend on emitter area matching to guarantee the gain vs. voltage control transfer curve specification.
A conventional PNP bipolar transistor structure is illustrated in FIG. 1, and designated generally at reference numeral 30. The bipolar transistor 30 is formed on a lightly doped p-type silicon substrate 2, which may include an isolation region formed therein, for example, a buried oxide layer 4. A p-type collector region 6 is formed over the buried oxide layer 4, and a collector-base interface 8 is defined above the buried oxide layer 4 by the formation of laterally spaced isolation regions 10. The isolation regions 10 may be field oxide (FOX) regions or shallow trench isolation (STI) regions of a generally amorphous microcrystalline structure. An n-type base layer 12 overlies the collector interface 8, which may have a dopant gradient. For example, the base layer 12 may comprise an SiGe strain layer with a graded profile SiGe layer and an intrinsic silicon buffer layer thereon (not shown), wherein the buffer layer serves to accommodate p-type dopant (e.g., boron), which diffuses from a polysilicon emitter 22 into the SiGe strain layer to form an emitter-base junction in the base layer 12. The base layer 12 generally comprises a base epitaxial portion (base epi) 12a with a microcrystalline structure conforming to that of the underlying silicon in the substrate 2, as well as polycrystalline (base poly) portions 12b overlying the isolation regions 10.
An emitter-base dielectric stack 14 is provided over the base layer 12 including a lower oxide layer 18 overlying the base layer 12, a nitride etch stop layer 20 overlying the oxide layer 18, and an upper oxide layer 16 overlying the nitride layer 20. A p-type polysilicon emitter region 22 contacts the base layer 12 through a contact region 24 in the layers 12, 18, and 20, respectively. In the transistor 30, the oxide layer 18 has a thickness 18a of about 150 Å to about 200 Å, the nitride layer 20 has a thickness 20a of between about 500 Å and about 1000 Å, and the oxide layer 16 has a thickness 16a of between about 500 Å and about 1000 Å. The oxide layer 18 typically includes a thermally grown oxide overlying the base layer 12, and may further comprise additional oxide deposited using a TEOS based deposition, so as to provide adequate thickness to about 150 to 200 Å. The thickness of the oxide layer 18 is driven by the need to protect the underlying base layer 12 during etching of the nitride layer 20 to form the emitter-base contact opening, while allowing sufficient overetching to completely etch the nitride thereof.
The structure of the transistor 30 may be created in a variety of ways. In the illustrated device 30, the base layer 12 is formed over the substrate 2 after the isolation regions 10 and the buried oxide layer 4 are created in the substrate 2. The base layer 12 is then deposited. Thereafter, the layers 18, 20, and 16 of the emitter-base dielectric stack 14 are deposited. The base layer 12 is then patterned by forming a patterned resist over the base layer 12 and dielectric stack layers, and the exposed portions of the base poly portions 12b outlying the transistor structure 30, and the dielectric stack above, are removed as illustrated in FIG. 1 using an etch process. Thereafter an opening is formed the stack 14 to define the contact region 24. Once the opening for the emitter-base contact is established, the emitter polysilicon 22 is deposited, after which boron is implanted into the polysilicon 22. The wafer is then heated to thermally diffuse the implanted boron from the polysilicon emitter 22 into the base epi 12a. An emitter-base junction is thus formed, which is ideally below the interface (poly/epi) of the emitter polysilicon 22 and the base epi 12a. In operation, the dielectric stack 14 provides a dielectric insulation between the base and emitter of the device 30 in areas other than the interface region 24.
In order to form an ideal bipolar transistor, the emitter-base junction dimensions need to be precise, so as to provide a predictable and repeatable emitter area. In this regard, better control over the junction dimensions facilitates better matching between devices in a given device, which is desirable in the fabrication of op-amps and other composite devices. Toward that end, the sidewalls of the opening in the insulator layers 18, 20, and 16 are ideally near vertical as illustrated in FIG. 1. However, forming vertical sidewalls requires a generally anisotropic etch process to form the opening for the emitter-base contact. Reactive ion etching (RIE) processes are generally recognized as having desirable anisotropic etching characteristics. Since the RIE processes involve both chemical etching as well as ionic bombardment, it is necessary to take precautions to prevent unwanted bombardment of the underlying base epi material 12a, or worse, etching straight though the dielectric stack and into the base layer.
Thus, an anisotropic RIE process is typically employed to etch an opening through the upper oxide layer 16, using the underlying nitride layer 20 as an etch stop. Thereafter, a second RIE is employed to remove the exposed nitride 20, leaving the thinner oxide layer 18 to protect the base epi 12a from the RIE ionic bombardment. The thinner oxide layer must also function as an etch stop for the nitride etch. Finally, a wet etch process is employed to remove the exposed portions of the layer 18, where the wet etching causes little or no damage to the base epi 12a. Thus, the nitride layer 20 is formed primarily to act as an etch stop layer for the first RIE process, and the lower oxide layer 18 serves as a nitride etch stop and protects the underlying base layer 12 from the adverse effects of the first and second RIE processes.
Difficulties occur when the dielectric stack is over etched and the etch proceeds into the base layer. Significant silicon lattice damage is induced, reducing transistor beta. If the stack is under etched, then only a central portion may at best be opened, and the emitter area is significantly reduced. The percent reduction is then a function of the overall patterned, or desired, emitter area, and not itself constant. Control over transistor matching is then lost or adversely impacted. Good control over the emitter opening etch is critical for control of general transistor matching. The conventional techniques for forming the emitter and the emitter-base contact and junction have heretofore not provided optimal control and repeatability for bipolar transistor emitter area and beta or gain, and further improvement is desirable to provide adequate component matching and process repeatability. Consequently there remains a need for improved methodologies for forming bipolar transistor emitter structures and emitter-base dielectric stacks in bipolar transistors, by which process repeatability and emitter area and beta control can be improved.